1. Field
The present invention relates to a non-volatile semiconductor storage device, and more particularly, to a non-volatile semiconductor storage device including memory strings each having non-volatile memory cells connected in series to each other and a memory system using the non-volatile semiconductor storage device.
2. Description of the Related Art
With an improvement in microfabrication technology, the length or width of a gate of a memory cell in a non-volatile semiconductor storage device, such as a NAND flash memory, has been significantly reduced. However, it is difficult to reduce the thickness of a gate insulating film of the memory cell in terms of the data storage reliability of the memory cell or voltage tolerance to data write and erase operations. As a result, when the memory cell is miniaturized, the amount of cell current flowing through the memory cell is reduced. In addition, in the NAND flash memory, with an increase in memory capacity, in a memory string having a plurality of memory cells connected in series to each other, the number of memory cells connected in series to each other tends to increase, and the amount of cell current flowing through the memory cell is decreased.
As described above, when the amount of cell current flowing through the memory cell is reduced, it is difficult to charge a bit line BL connected to each memory string within a predetermined time during an erase verification operation that verifies the erase state of the memory cell, even when data has been erased from all the memory cells in the memory string.
Further, in the NAND flash memory, when the memory cell is miniaturized and the capacity thereof is increased, there is a large difference in write characteristics between memory cells arranged at both ends of the memory string and at the middle of the memory string. JP-A-2005-235260 discloses a NAND flash memory that unifies the write characteristics. In the NAND flash memory, memory cells adjacent to a bit-line-side select gate and a source-side select gate connected to both ends of a memory string are used as dummy cells and a plurality of memory cells are connected between the two dummy cells. Since the dummy cells do not store information, the dummy cells are treated as non-selection cells during write and read operations all the time. The dummy cells make it possible to perform the write operation on the memory cells interposed between the dummy cells under the uniform bias conditions.
Furthermore, in the NAND flash memory, when the cell current is reduced due to the miniaturization of the memory cell, the low-voltage margin of the memory cell is reduced, which causes an erase fail during an erase verification operation. JP-A-2006-54036 discloses an erase scheme and a non-volatile memory device that prevent the erase fail during the erase verification operation. In the erase scheme and the non-volatile memory device, a first read voltage is applied to some memory cells in a memory string during the erase verification operation, and a second read voltage that is higher than the first read voltage is applied to the other memory cells. In this state, a first erase verification operation is performed. In addition, the second read voltage is applied to some memory cells, and the first read voltage is applied to the other memory cells. In this state, a second erase verification operation is performed. In this way, the reliability of the erase verification operation is improved.